#redirect -file -tee ./log/export.log {source ./scripts/export.tcl}
################################
# setup and proc
# ##############################
source -e -v user_scripts/global_setup.tcl
source -e -v user_scripts/block_setup.tcl
source -e -v user_scripts/loadInnovus.tcl

set current_step "export"

set report_dir "reports/${current_step}"
if {![file exist $report_dir]} {file mkdir $report_dir}

#####################################
# open design
# ##################################
restoreDesign ${DESIGN_LIBRARY}/${DESIGN_NAME}.${WRITE_DATA_STEP_NAME}.dat $DESIGN_NAME

# common setting
source -e -v user_scripts/common_setting.tcl



############################################
# export
############################################
foreach type $WRITE_DATA_TYPE_LIST {
		set write_type($type) true
}

if {$REMOVE_EMPTY_MODULE} {
		puts "INFO: start to delete empty module"
		deleteEmptyModule
}

setStreamOutMode -SEvianames true -specifyViaName %t_%v -virtualConnection false

#gds
if {[info exist write_type(gds)]} {
		set write_gds_cmd "streamOut -dieAreaAsBoundary -units 1000 -mode ALL -outputMacros -structureName ${DESIGN_NAME} ${OUTPUTS_DIR}/${DESIGN_NAME}.gds"
		if {[file exists $WRITE_GDS_LAYER_MAP_FILE]} {
				lappend write_gds_cmd -mapFile $WRITE_GDS_LAYER_MAP_FILE
		}
		set GDS_FILE ""
		foreach gds $STDCELL_GDS_FILE {set GDS_FILE [concat $GDS_FILE $gds]}
		foreach gds $MACRO_GDS_FILE {set GDS_FILE [concat $GDS_FILE $gds]}
		foreach gds $SUB_BLOCK_GDS_FILE {set GDS_FILE [concat $GDS_FILE $gds]}
		if {[llength $GDS_FILE] != 0} {lappend write_gds_cmd -merge $GDS_FILE -uniquifyCellNames}
		Puts "INFO: $write_gds_cmd"
		eval $write_gds_cmd
}

#pg netlist
set DCAP_CELLS "FILE128HM FILE64HM FILE32HM FILE16HM FILE8HM FILE4HM FILE3HM"
#set TAP_CELL FILLTIE3_A9TRULP_C40_W3
set FILLER_CELLS "FIL64HM FIL32HM FIL16HM FIL8HM FIL4HM FIL2HM FIL1HM"
if {[info exist write_type(pg_verilog)]} {
		remove_assigns
		set includeCellList ""
		set includeCellList [concat $includeCellList $DCAP_CELLS]
#		set includeCellList [concat $includeCellList $TAP_CELL]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IVDDIO]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IVSSIO]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IVDD]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IVSS]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name ICORNER]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IUMA]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name IDCLAMPC]]
		set includeCellList [concat $includeCellList [dbGet -e head.libCells.name PC_C]]

		set excludeCellList ""
		set excludeCellList [concat $excludeCellList $FILLER_CELLS]
#		set excludeCellList [concat $excludeCellList $TAP_CELL]
#		set excludeCellList [concat $excludeCellList [dbGet -e head.libCells.name ICORNERFS]]
		set excludeCellList [concat $excludeCellList [dbGet -e head.libCells.name IFILLER*]]

		saveNetlist -excludeLeafCell -includePowerGround -includePhysicalCell $includeCellList -excludeCellInst $excludeCellList -flattenBus ${OUTPUTS_DIR}/${DESIGN_NAME}.pg.v
		saveNetlist -excludeLeafCell  -includePhysicalCell $includeCellList -excludeCellInst $excludeCellList -flattenBus ${OUTPUTS_DIR}/${DESIGN_NAME}.lvs.v
}

#def
if {[info exist write_type(def)]} {
		set defOutLefVia 1
		defOut -unit 2000 -usedVia -routing ${OUTPUTS_DIR}/${DESIGN_NAME}.def.gz
}

#def for signoff RC extraction
if {[info exist write_type(starrc_def)]} {
		defOut -unit 2000 -usedVia -routing -wrongway_routing_as_specialroute -skip_trimmetal_layer ${OUTPUTS_DIR}/${DESIGN_NAME}.starrc.def.gz
}

#lef
if {$WRITE_LEF_WITH_ANTENNA} {verifyProcessAntenna}

set top_metal_layer $MAX_ROUTING_LAYER
foreach layer $PG_PIN_LAYER {
		if {[dbGet [dbGet -p head.layers.name $layer].num] > [dbGet [dbGet -p head.layers.name $top_metal_layer].num]} {
				set top_metal_layer $layer
		}
}

if {[info exist write_type(lef)]} {
		write_lef_abstract \
		  -noCutObs \
		  -stripePin \
		  -PGpinLayers $PG_PIN_LAYER \
		  -specifyTopLayer $top_metal_layer \
		  ${OUTPUTS_DIR}/${DESIGN_NAME}.lef
}

#tech lef
if {[info exist write_type(tech_lef)]} {
		write_lef_library -tech_only ${OUTPUTS_DIR}/${DESIGN_NAME}.tech.lef
}

#verilog
if {[info exist write_type(verilog)]} {
		saveNetlist -excludeLeafCell ${OUTPUTS_DIR}/${DESIGN_NAME}.v
}

#spef
if {[info exist write_type(spef)]} {
		extractRC
		foreach corner [all_rc_corners] {
				rcOut -rc_corner $corner -spef ${OUTPUTS_DIR}/${DESIGN_NAME}.${corner}.spef.gz
		}
}

#sdc

#etm
if {[info exist write_type(etm)]} {
		source -e -v user_scripts/write_etm.tcl
}


# design info
echo "Design Name: $DESIGN_NAME" > ${OUTPUTS_DIR}/README
echo "Write Step: $WRITE_DATA_STEP_NAME" > ${OUTPUTS_DIR}/README
echo "Write Files: $WRITE_DATA_TYPE_LIST" > ${OUTPUTS_DIR}/README
echo "Database: [file normalize ${DESIGN_LIBRARY}/$DESIGN_NAME.${WRITE_DATA_STEP_NAME}.dat]" > ${OUTPUTS_DIR}/README
echo "Block Setup: [file normalize ./user_scripts/block_setup.tcl]" > ${OUTPUTS_DIR}/README


date > ${current_step}

exit






